URL https://opencores.org/ocsvn/wishbone_bfm/wishbone_bfm/trunk

Subversion Repositories wishbone_bfm

[/] [wishbone_bfm/] [branches/] [avendor/] [rtl/] [wb_master.vhd] - Rev 15

Rev	Log message	Author	Age	Path
15	New directory structure.	root	5688d 19h	/wishbone_bfm/branches/avendor/rtl/wb_master.vhd
12	add block read and write 32 commands	amulcock	6072d 10h	/wishbone_bfm/branches/avendor/rtl/wb_master.vhd
10	Add rmw 32 cycle	amulcock	6078d 08h	/wishbone_bfm/branches/avendor/rtl/wb_master.vhd
8	change read procedure to return a variable , not a signal, as had a 'delta' problem.	amulcock	6078d 09h	/wishbone_bfm/branches/avendor/rtl/wb_master.vhd
6	Add 32 bit slave memmory into the test bench architecture, and test out R32 and W32 commands	amulcock	6079d 12h	/wishbone_bfm/branches/avendor/rtl/wb_master.vhd
2	Initial ideas, support W32 and R32 commands	amulcock	6080d 10h	/wishbone_bfm/branches/avendor/rtl/wb_master.vhd