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[/] [xgate/] [trunk/] [README.txt] - Rev 81

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Rev	Log message	Author	Age	Path
77	Documentation update	rehayes	5284d 03h	/xgate/trunk/README.txt
76	Updated xgate_risc.v for xlink synthesis warnings.	rehayes	5307d 04h	/xgate/trunk/README.txt
74	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5312d 05h	/xgate/trunk/README.txt
71	Added irq bypass registers to rtl, testbench and doc.	rehayes	5313d 08h	/xgate/trunk/README.txt
66	Fix testbench and RISC core related to debug mode and wait states.	rehayes	5333d 04h	/xgate/trunk/README.txt
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5350d 03h	/xgate/trunk/README.txt
58	WISHBONE Bus update.	rehayes	5402d 03h	/xgate/trunk/README.txt
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5418d 07h	/xgate/trunk/README.txt
51	Corrections to ADC and SBC instructions, First pass at documentaion instruction set details	rehayes	5434d 04h	/xgate/trunk/README.txt
44	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5468d 01h	/xgate/trunk/README.txt
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5469d 04h	/xgate/trunk/README.txt
38	Nov 9 2009 update notes	rehayes	5497d 08h	/xgate/trunk/README.txt
23	Oct 7, 2009 Update	rehayes	5530d 03h	/xgate/trunk/README.txt
14	Sept 23 2009 Change update	rehayes	5544d 04h	/xgate/trunk/README.txt
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5557d 04h	/xgate/trunk/README.txt
2	Initial Checkin	rehayes	5565d 02h	/xgate/trunk/README.txt

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