URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [bench/] [verilog/] [debug_test.v] - Rev 62

Rev	Log message	Author	Age	Path
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5409d 03h	/xgate/trunk/bench/verilog/debug_test.v
50	incremental update to match status bit changes	rehayes	5425d 00h	/xgate/trunk/bench/verilog/debug_test.v
19	Verilog memory image for testing	rehayes	5521d 00h	/xgate/trunk/bench/verilog/debug_test.v