URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Rev 40

Rev	Log message	Author	Age	Path
36	Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls.	rehayes	5388d 18h	/xgate/trunk/bench/verilog/tst_bench_top.v
21	Added timeout, total error count, and XGCHN test	rehayes	5421d 14h	/xgate/trunk/bench/verilog/tst_bench_top.v
11	Update with Single Step debuging test	rehayes	5435d 14h	/xgate/trunk/bench/verilog/tst_bench_top.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5448d 14h	/xgate/trunk/bench/verilog/tst_bench_top.v
2	Initial Checkin	rehayes	5456d 12h	/xgate/trunk/bench/verilog/tst_bench_top.v