URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Rev 62

Rev	Log message	Author	Age	Path
62	Cleanup implicit wire declarations.	rehayes	5334d 00h	/xgate/trunk/bench/verilog/tst_bench_top.v
60	Add ability at insert wait states on RAM access	rehayes	5341d 00h	/xgate/trunk/bench/verilog/tst_bench_top.v
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5409d 04h	/xgate/trunk/bench/verilog/tst_bench_top.v
50	incremental update to match status bit changes	rehayes	5425d 00h	/xgate/trunk/bench/verilog/tst_bench_top.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5460d 00h	/xgate/trunk/bench/verilog/tst_bench_top.v
36	Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls.	rehayes	5488d 05h	/xgate/trunk/bench/verilog/tst_bench_top.v
21	Added timeout, total error count, and XGCHN test	rehayes	5521d 00h	/xgate/trunk/bench/verilog/tst_bench_top.v
11	Update with Single Step debuging test	rehayes	5535d 00h	/xgate/trunk/bench/verilog/tst_bench_top.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5548d 00h	/xgate/trunk/bench/verilog/tst_bench_top.v
2	Initial Checkin	rehayes	5555d 22h	/xgate/trunk/bench/verilog/tst_bench_top.v