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[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Rev 75

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73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5312d 10h /xgate/trunk/bench/verilog/tst_bench_top.v
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5313d 13h /xgate/trunk/bench/verilog/tst_bench_top.v
65 Parameterize delays based on number of RAM wait states. rehayes 5333d 09h /xgate/trunk/bench/verilog/tst_bench_top.v
62 Cleanup implicit wire declarations. rehayes 5343d 09h /xgate/trunk/bench/verilog/tst_bench_top.v
60 Add ability at insert wait states on RAM access rehayes 5350d 08h /xgate/trunk/bench/verilog/tst_bench_top.v
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5418d 12h /xgate/trunk/bench/verilog/tst_bench_top.v
50 incremental update to match status bit changes rehayes 5434d 08h /xgate/trunk/bench/verilog/tst_bench_top.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5469d 08h /xgate/trunk/bench/verilog/tst_bench_top.v
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5497d 13h /xgate/trunk/bench/verilog/tst_bench_top.v
21 Added timeout, total error count, and XGCHN test rehayes 5530d 08h /xgate/trunk/bench/verilog/tst_bench_top.v
11 Update with Single Step debuging test rehayes 5544d 09h /xgate/trunk/bench/verilog/tst_bench_top.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5557d 09h /xgate/trunk/bench/verilog/tst_bench_top.v
2 Initial Checkin rehayes 5565d 06h /xgate/trunk/bench/verilog/tst_bench_top.v

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