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[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Rev 94

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94 Update irq test to check all interrupts, add sync reset test. All this to improve code coverage. rehayes 4814d 13h /xgate/trunk/bench/verilog/tst_bench_top.v
89 Code cleanup. rehayes 4828d 13h /xgate/trunk/bench/verilog/tst_bench_top.v
86 Add JTAG test tasks rehayes 5028d 12h /xgate/trunk/bench/verilog/tst_bench_top.v
82 Added debug module to assist in software debugging. rehayes 5303d 16h /xgate/trunk/bench/verilog/tst_bench_top.v
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5393d 19h /xgate/trunk/bench/verilog/tst_bench_top.v
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5394d 22h /xgate/trunk/bench/verilog/tst_bench_top.v
65 Parameterize delays based on number of RAM wait states. rehayes 5414d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
62 Cleanup implicit wire declarations. rehayes 5424d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
60 Add ability at insert wait states on RAM access rehayes 5431d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5499d 21h /xgate/trunk/bench/verilog/tst_bench_top.v
50 incremental update to match status bit changes rehayes 5515d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5550d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5578d 22h /xgate/trunk/bench/verilog/tst_bench_top.v
21 Added timeout, total error count, and XGCHN test rehayes 5611d 17h /xgate/trunk/bench/verilog/tst_bench_top.v
11 Update with Single Step debuging test rehayes 5625d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5638d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
2 Initial Checkin rehayes 5646d 16h /xgate/trunk/bench/verilog/tst_bench_top.v

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