OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Rev 95

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
94 Update irq test to check all interrupts, add sync reset test. All this to improve code coverage. rehayes 4724d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
89 Code cleanup. rehayes 4738d 17h /xgate/trunk/bench/verilog/tst_bench_top.v
86 Add JTAG test tasks rehayes 4938d 16h /xgate/trunk/bench/verilog/tst_bench_top.v
82 Added debug module to assist in software debugging. rehayes 5213d 20h /xgate/trunk/bench/verilog/tst_bench_top.v
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5303d 23h /xgate/trunk/bench/verilog/tst_bench_top.v
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5305d 03h /xgate/trunk/bench/verilog/tst_bench_top.v
65 Parameterize delays based on number of RAM wait states. rehayes 5324d 22h /xgate/trunk/bench/verilog/tst_bench_top.v
62 Cleanup implicit wire declarations. rehayes 5334d 22h /xgate/trunk/bench/verilog/tst_bench_top.v
60 Add ability at insert wait states on RAM access rehayes 5341d 22h /xgate/trunk/bench/verilog/tst_bench_top.v
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5410d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
50 incremental update to match status bit changes rehayes 5425d 22h /xgate/trunk/bench/verilog/tst_bench_top.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5460d 22h /xgate/trunk/bench/verilog/tst_bench_top.v
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5489d 02h /xgate/trunk/bench/verilog/tst_bench_top.v
21 Added timeout, total error count, and XGCHN test rehayes 5521d 22h /xgate/trunk/bench/verilog/tst_bench_top.v
11 Update with Single Step debuging test rehayes 5535d 22h /xgate/trunk/bench/verilog/tst_bench_top.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5548d 22h /xgate/trunk/bench/verilog/tst_bench_top.v
2 Initial Checkin rehayes 5556d 20h /xgate/trunk/bench/verilog/tst_bench_top.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.