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[/] [xgate/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Rev 62

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Rev Log message Author Age Path
35 Add byte lane select input to all tasks rehayes 5488d 05h /xgate/trunk/bench/verilog/wb_master_model.v
27 Subversion test, no actual code changes rehayes 5512d 22h /xgate/trunk/bench/verilog/wb_master_model.v
20 Added event signal for compare error tracking in top level test bench. rehayes 5521d 00h /xgate/trunk/bench/verilog/wb_master_model.v
2 Initial Checkin rehayes 5555d 22h /xgate/trunk/bench/verilog/wb_master_model.v

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