URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_regs.v] - Rev 67

Rev	Log message	Author	Age	Path
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5313d 08h	/xgate/trunk/rtl/verilog/xgate_regs.v
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5418d 07h	/xgate/trunk/rtl/verilog/xgate_regs.v
42	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5468d 01h	/xgate/trunk/rtl/verilog/xgate_regs.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5469d 03h	/xgate/trunk/rtl/verilog/xgate_regs.v
24	Delete unused inputs	rehayes	5524d 06h	/xgate/trunk/rtl/verilog/xgate_regs.v
15	Fix R1 load at boot up, add debug features	rehayes	5543d 01h	/xgate/trunk/rtl/verilog/xgate_regs.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5544d 03h	/xgate/trunk/rtl/verilog/xgate_regs.v
2	Initial Checkin	rehayes	5565d 01h	/xgate/trunk/rtl/verilog/xgate_regs.v