URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_regs.v] - Rev 85

Rev	Log message	Author	Age	Path
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5200d 14h	/xgate/trunk/rtl/verilog/xgate_regs.v
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5201d 17h	/xgate/trunk/rtl/verilog/xgate_regs.v
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5306d 16h	/xgate/trunk/rtl/verilog/xgate_regs.v
42	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5356d 10h	/xgate/trunk/rtl/verilog/xgate_regs.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5357d 12h	/xgate/trunk/rtl/verilog/xgate_regs.v
24	Delete unused inputs	rehayes	5412d 15h	/xgate/trunk/rtl/verilog/xgate_regs.v
15	Fix R1 load at boot up, add debug features	rehayes	5431d 10h	/xgate/trunk/rtl/verilog/xgate_regs.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5432d 12h	/xgate/trunk/rtl/verilog/xgate_regs.v
2	Initial Checkin	rehayes	5453d 10h	/xgate/trunk/rtl/verilog/xgate_regs.v