URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_regs.v] - Rev 92

Rev	Log message	Author	Age	Path
92	Add sync reset to bypass register.	rehayes	4611d 21h	/xgate/trunk/rtl/verilog/xgate_regs.v
89	Code cleanup.	rehayes	4625d 20h	/xgate/trunk/rtl/verilog/xgate_regs.v
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5191d 03h	/xgate/trunk/rtl/verilog/xgate_regs.v
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5192d 06h	/xgate/trunk/rtl/verilog/xgate_regs.v
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5297d 05h	/xgate/trunk/rtl/verilog/xgate_regs.v
42	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5346d 23h	/xgate/trunk/rtl/verilog/xgate_regs.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5348d 01h	/xgate/trunk/rtl/verilog/xgate_regs.v
24	Delete unused inputs	rehayes	5403d 04h	/xgate/trunk/rtl/verilog/xgate_regs.v
15	Fix R1 load at boot up, add debug features	rehayes	5421d 23h	/xgate/trunk/rtl/verilog/xgate_regs.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5423d 01h	/xgate/trunk/rtl/verilog/xgate_regs.v
2	Initial Checkin	rehayes	5443d 23h	/xgate/trunk/rtl/verilog/xgate_regs.v