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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_regs.v] - Rev 96

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Rev Log message Author Age Path
96 Fix lint problems, change lowest interrupt vector from 0 to 1. rehayes 4203d 16h /xgate/trunk/rtl/verilog/xgate_regs.v
92 Add sync reset to bypass register. rehayes 4594d 19h /xgate/trunk/rtl/verilog/xgate_regs.v
89 Code cleanup. rehayes 4608d 18h /xgate/trunk/rtl/verilog/xgate_regs.v
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5174d 01h /xgate/trunk/rtl/verilog/xgate_regs.v
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5175d 04h /xgate/trunk/rtl/verilog/xgate_regs.v
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5280d 03h /xgate/trunk/rtl/verilog/xgate_regs.v
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5329d 21h /xgate/trunk/rtl/verilog/xgate_regs.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5330d 23h /xgate/trunk/rtl/verilog/xgate_regs.v
24 Delete unused inputs rehayes 5386d 02h /xgate/trunk/rtl/verilog/xgate_regs.v
15 Fix R1 load at boot up, add debug features rehayes 5404d 21h /xgate/trunk/rtl/verilog/xgate_regs.v
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5405d 23h /xgate/trunk/rtl/verilog/xgate_regs.v
2 Initial Checkin rehayes 5426d 21h /xgate/trunk/rtl/verilog/xgate_regs.v

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