| Rev |
Log message |
Author |
Age |
Path |
| 98 |
Fixed PC underflow detect error when loading PC at thread startup. |
rehayes |
4281d 17h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 97 |
Fix lint problems, change lowest interrupt vector from 0 to 1.\nDetect program counter underflow/overflow as a software error. |
rehayes |
4301d 04h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 89 |
Code cleanup. |
rehayes |
4706d 07h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 75 |
Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 |
rehayes |
5266d 13h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 72 |
Code cleanup, eliminated index 0 of input and output interrupts. |
rehayes |
5271d 14h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 67 |
Added irq bypass function and controll registers. Made lowest interrupt index highest priority. |
rehayes |
5272d 17h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 64 |
Fixed more bugs related to wait states and debug mode. |
rehayes |
5292d 13h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 59 |
Fix bug in entering DEBUG mode from WB bus command |
rehayes |
5309d 12h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 53 |
Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. |
rehayes |
5377d 16h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 47 |
Fix status bit error in ADC and SBC instruction, fix error in thread startup. |
rehayes |
5393d 13h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 41 |
Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection |
rehayes |
5428d 12h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 40 |
Update for single program counter adder |
rehayes |
5448d 15h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 34 |
minor changes related to wishbone master interface |
rehayes |
5456d 17h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 31 |
Cleanup for MAX_CHANNEL bus |
rehayes |
5468d 12h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 26 |
Add synopsys commands, add else defaults for semphore state machine. |
rehayes |
5483d 13h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 17 |
Additions for XGCHID debug commands |
rehayes |
5489d 12h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 15 |
Fix R1 load at boot up, add debug features |
rehayes |
5502d 10h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 12 |
Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits |
rehayes |
5503d 12h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 5 |
Update for memory wait states, testbench and instruction decoder simplified for synthesis |
rehayes |
5516d 12h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
| 2 |
Initial Checkin |
rehayes |
5524d 10h |
/xgate/trunk/rtl/verilog/xgate_risc.v |
