URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_risc.v] - Rev 12

Rev	Log message	Author	Age	Path
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5398d 12h	/xgate/trunk/rtl/verilog/xgate_risc.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5411d 12h	/xgate/trunk/rtl/verilog/xgate_risc.v
2	Initial Checkin	rehayes	5419d 10h	/xgate/trunk/rtl/verilog/xgate_risc.v