URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_risc.v] - Rev 29

Rev	Log message	Author	Age	Path
26	Add synopsys commands, add else defaults for semphore state machine.	rehayes	5524d 21h	/xgate/trunk/rtl/verilog/xgate_risc.v
17	Additions for XGCHID debug commands	rehayes	5530d 20h	/xgate/trunk/rtl/verilog/xgate_risc.v
15	Fix R1 load at boot up, add debug features	rehayes	5543d 18h	/xgate/trunk/rtl/verilog/xgate_risc.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5544d 20h	/xgate/trunk/rtl/verilog/xgate_risc.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5557d 20h	/xgate/trunk/rtl/verilog/xgate_risc.v
2	Initial Checkin	rehayes	5565d 18h	/xgate/trunk/rtl/verilog/xgate_risc.v