OpenCores

URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_risc.v] - Rev 56

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5425d 08h	/xgate/trunk/rtl/verilog/xgate_risc.v
47	Fix status bit error in ADC and SBC instruction, fix error in thread startup.	rehayes	5441d 05h	/xgate/trunk/rtl/verilog/xgate_risc.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5476d 05h	/xgate/trunk/rtl/verilog/xgate_risc.v
40	Update for single program counter adder	rehayes	5496d 07h	/xgate/trunk/rtl/verilog/xgate_risc.v
34	minor changes related to wishbone master interface	rehayes	5504d 09h	/xgate/trunk/rtl/verilog/xgate_risc.v
31	Cleanup for MAX_CHANNEL bus	rehayes	5516d 05h	/xgate/trunk/rtl/verilog/xgate_risc.v
26	Add synopsys commands, add else defaults for semphore state machine.	rehayes	5531d 06h	/xgate/trunk/rtl/verilog/xgate_risc.v
17	Additions for XGCHID debug commands	rehayes	5537d 05h	/xgate/trunk/rtl/verilog/xgate_risc.v
15	Fix R1 load at boot up, add debug features	rehayes	5550d 03h	/xgate/trunk/rtl/verilog/xgate_risc.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5551d 05h	/xgate/trunk/rtl/verilog/xgate_risc.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5564d 05h	/xgate/trunk/rtl/verilog/xgate_risc.v
2	Initial Checkin	rehayes	5572d 03h	/xgate/trunk/rtl/verilog/xgate_risc.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.