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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_risc.v] - Rev 62

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Rev Log message Author Age Path
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5355d 18h /xgate/trunk/rtl/verilog/xgate_risc.v
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5423d 22h /xgate/trunk/rtl/verilog/xgate_risc.v
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5439d 19h /xgate/trunk/rtl/verilog/xgate_risc.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5474d 18h /xgate/trunk/rtl/verilog/xgate_risc.v
40 Update for single program counter adder rehayes 5494d 21h /xgate/trunk/rtl/verilog/xgate_risc.v
34 minor changes related to wishbone master interface rehayes 5502d 23h /xgate/trunk/rtl/verilog/xgate_risc.v
31 Cleanup for MAX_CHANNEL bus rehayes 5514d 18h /xgate/trunk/rtl/verilog/xgate_risc.v
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5529d 19h /xgate/trunk/rtl/verilog/xgate_risc.v
17 Additions for XGCHID debug commands rehayes 5535d 18h /xgate/trunk/rtl/verilog/xgate_risc.v
15 Fix R1 load at boot up, add debug features rehayes 5548d 16h /xgate/trunk/rtl/verilog/xgate_risc.v
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5549d 18h /xgate/trunk/rtl/verilog/xgate_risc.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5562d 19h /xgate/trunk/rtl/verilog/xgate_risc.v
2 Initial Checkin rehayes 5570d 16h /xgate/trunk/rtl/verilog/xgate_risc.v

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