OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_risc.v] - Rev 77

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5172d 12h /xgate/trunk/rtl/verilog/xgate_risc.v
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5177d 13h /xgate/trunk/rtl/verilog/xgate_risc.v
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5178d 17h /xgate/trunk/rtl/verilog/xgate_risc.v
64 Fixed more bugs related to wait states and debug mode. rehayes 5198d 12h /xgate/trunk/rtl/verilog/xgate_risc.v
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5215d 12h /xgate/trunk/rtl/verilog/xgate_risc.v
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5283d 15h /xgate/trunk/rtl/verilog/xgate_risc.v
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5299d 12h /xgate/trunk/rtl/verilog/xgate_risc.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5334d 12h /xgate/trunk/rtl/verilog/xgate_risc.v
40 Update for single program counter adder rehayes 5354d 15h /xgate/trunk/rtl/verilog/xgate_risc.v
34 minor changes related to wishbone master interface rehayes 5362d 17h /xgate/trunk/rtl/verilog/xgate_risc.v
31 Cleanup for MAX_CHANNEL bus rehayes 5374d 12h /xgate/trunk/rtl/verilog/xgate_risc.v
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5389d 13h /xgate/trunk/rtl/verilog/xgate_risc.v
17 Additions for XGCHID debug commands rehayes 5395d 12h /xgate/trunk/rtl/verilog/xgate_risc.v
15 Fix R1 load at boot up, add debug features rehayes 5408d 10h /xgate/trunk/rtl/verilog/xgate_risc.v
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5409d 12h /xgate/trunk/rtl/verilog/xgate_risc.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5422d 12h /xgate/trunk/rtl/verilog/xgate_risc.v
2 Initial Checkin rehayes 5430d 10h /xgate/trunk/rtl/verilog/xgate_risc.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.