URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Rev 56

Rev	Log message	Author	Age	Path
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5425d 09h	/xgate/trunk/rtl/verilog/xgate_top.v
43	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5475d 03h	/xgate/trunk/rtl/verilog/xgate_top.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5476d 05h	/xgate/trunk/rtl/verilog/xgate_top.v
34	minor changes related to wishbone master interface	rehayes	5504d 10h	/xgate/trunk/rtl/verilog/xgate_top.v
30	Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus	rehayes	5516d 05h	/xgate/trunk/rtl/verilog/xgate_top.v
25	Fix connected net name	rehayes	5531d 07h	/xgate/trunk/rtl/verilog/xgate_top.v
17	Additions for XGCHID debug commands	rehayes	5537d 05h	/xgate/trunk/rtl/verilog/xgate_top.v
15	Fix R1 load at boot up, add debug features	rehayes	5550d 03h	/xgate/trunk/rtl/verilog/xgate_top.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5551d 05h	/xgate/trunk/rtl/verilog/xgate_top.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5564d 06h	/xgate/trunk/rtl/verilog/xgate_top.v
2	Initial Checkin	rehayes	5572d 03h	/xgate/trunk/rtl/verilog/xgate_top.v