URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Rev 58

Rev	Log message	Author	Age	Path
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5471d 17h	/xgate/trunk/rtl/verilog/xgate_top.v
43	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5521d 11h	/xgate/trunk/rtl/verilog/xgate_top.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5522d 13h	/xgate/trunk/rtl/verilog/xgate_top.v
34	minor changes related to wishbone master interface	rehayes	5550d 18h	/xgate/trunk/rtl/verilog/xgate_top.v
30	Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus	rehayes	5562d 13h	/xgate/trunk/rtl/verilog/xgate_top.v
25	Fix connected net name	rehayes	5577d 14h	/xgate/trunk/rtl/verilog/xgate_top.v
17	Additions for XGCHID debug commands	rehayes	5583d 13h	/xgate/trunk/rtl/verilog/xgate_top.v
15	Fix R1 load at boot up, add debug features	rehayes	5596d 11h	/xgate/trunk/rtl/verilog/xgate_top.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5597d 13h	/xgate/trunk/rtl/verilog/xgate_top.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5610d 13h	/xgate/trunk/rtl/verilog/xgate_top.v
2	Initial Checkin	rehayes	5618d 11h	/xgate/trunk/rtl/verilog/xgate_top.v