URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Rev 59

Rev	Log message	Author	Age	Path
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5401d 15h	/xgate/trunk/rtl/verilog/xgate_top.v
43	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5451d 09h	/xgate/trunk/rtl/verilog/xgate_top.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5452d 11h	/xgate/trunk/rtl/verilog/xgate_top.v
34	minor changes related to wishbone master interface	rehayes	5480d 16h	/xgate/trunk/rtl/verilog/xgate_top.v
30	Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus	rehayes	5492d 11h	/xgate/trunk/rtl/verilog/xgate_top.v
25	Fix connected net name	rehayes	5507d 13h	/xgate/trunk/rtl/verilog/xgate_top.v
17	Additions for XGCHID debug commands	rehayes	5513d 11h	/xgate/trunk/rtl/verilog/xgate_top.v
15	Fix R1 load at boot up, add debug features	rehayes	5526d 09h	/xgate/trunk/rtl/verilog/xgate_top.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5527d 11h	/xgate/trunk/rtl/verilog/xgate_top.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5540d 12h	/xgate/trunk/rtl/verilog/xgate_top.v
2	Initial Checkin	rehayes	5548d 09h	/xgate/trunk/rtl/verilog/xgate_top.v