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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Rev 89

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Rev Log message Author Age Path
89 Code cleanup. rehayes 4828d 11h /xgate/trunk/rtl/verilog/xgate_top.v
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5393d 18h /xgate/trunk/rtl/verilog/xgate_top.v
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5394d 21h /xgate/trunk/rtl/verilog/xgate_top.v
63 Remove historical output ports that are no longer used. rehayes 5424d 17h /xgate/trunk/rtl/verilog/xgate_top.v
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5499d 20h /xgate/trunk/rtl/verilog/xgate_top.v
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5549d 14h /xgate/trunk/rtl/verilog/xgate_top.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5550d 16h /xgate/trunk/rtl/verilog/xgate_top.v
34 minor changes related to wishbone master interface rehayes 5578d 21h /xgate/trunk/rtl/verilog/xgate_top.v
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5590d 16h /xgate/trunk/rtl/verilog/xgate_top.v
25 Fix connected net name rehayes 5605d 18h /xgate/trunk/rtl/verilog/xgate_top.v
17 Additions for XGCHID debug commands rehayes 5611d 16h /xgate/trunk/rtl/verilog/xgate_top.v
15 Fix R1 load at boot up, add debug features rehayes 5624d 15h /xgate/trunk/rtl/verilog/xgate_top.v
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5625d 17h /xgate/trunk/rtl/verilog/xgate_top.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5638d 17h /xgate/trunk/rtl/verilog/xgate_top.v
2 Initial Checkin rehayes 5646d 15h /xgate/trunk/rtl/verilog/xgate_top.v

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