URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbm_bus.v] - Rev 100

Rev	Log message	Author	Age	Path
96	Fix lint problems, change lowest interrupt vector from 0 to 1.	rehayes	4206d 18h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
89	Code cleanup.	rehayes	4611d 20h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5283d 05h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
34	minor changes related to wishbone master interface	rehayes	5362d 06h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
29	Added some constant assigments, still needs more work to complete	rehayes	5374d 01h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5409d 01h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v