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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbm_bus.v] - Rev 42

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34 minor changes related to wishbone master interface rehayes 5517d 15h /xgate/trunk/rtl/verilog/xgate_wbm_bus.v
29 Added some constant assigments, still needs more work to complete rehayes 5529d 11h /xgate/trunk/rtl/verilog/xgate_wbm_bus.v
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5564d 11h /xgate/trunk/rtl/verilog/xgate_wbm_bus.v

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