URL https://opencores.org/ocsvn/xgate/xgate/trunk

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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbm_bus.v] - Rev 53

Rev	Log message	Author	Age	Path
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5267d 15h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
34	minor changes related to wishbone master interface	rehayes	5346d 16h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
29	Added some constant assigments, still needs more work to complete	rehayes	5358d 11h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5393d 12h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v