URL https://opencores.org/ocsvn/xgate/xgate/trunk

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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbm_bus.v] - Rev 89

Rev	Log message	Author	Age	Path
89	Code cleanup.	rehayes	4746d 16h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5418d 01h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
34	minor changes related to wishbone master interface	rehayes	5497d 02h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
29	Added some constant assigments, still needs more work to complete	rehayes	5508d 21h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5543d 22h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v