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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbs_bus.v] - Rev 53

Rev	Log message	Author	Age	Path
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5418d 03h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5468d 23h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
17	Additions for XGCHID debug commands	rehayes	5529d 23h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5556d 23h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
2	Initial Checkin	rehayes	5564d 21h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v