URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbs_bus.v] - Rev 63

Rev	Log message	Author	Age	Path
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5391d 19h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5407d 20h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5458d 16h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
17	Additions for XGCHID debug commands	rehayes	5519d 16h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5546d 17h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
2	Initial Checkin	rehayes	5554d 15h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v