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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbs_bus.v] - Rev 74

Rev	Log message	Author	Age	Path
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5290d 12h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5291d 15h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5380d 13h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5396d 14h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5447d 10h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
17	Additions for XGCHID debug commands	rehayes	5508d 10h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5535d 10h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
2	Initial Checkin	rehayes	5543d 08h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v