URL https://opencores.org/ocsvn/xgate/xgate/trunk

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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbs_bus.v] - Rev 97

Rev	Log message	Author	Age	Path
96	Fix lint problems, change lowest interrupt vector from 0 to 1.	rehayes	4257d 17h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
89	Code cleanup.	rehayes	4662d 19h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5228d 02h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5229d 05h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5318d 03h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5334d 04h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5385d 00h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
17	Additions for XGCHID debug commands	rehayes	5446d 00h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5473d 01h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
2	Initial Checkin	rehayes	5480d 22h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v