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[/] [xge_mac/] [trunk/] [rtl/] [auto_verilog.sh] - Rev 22

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21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4384d 02h /xge_mac/trunk/rtl/auto_verilog.sh
20 Updates for Xilinx synthesis antanguay 4673d 20h /xge_mac/trunk/rtl/auto_verilog.sh
7 New directory structure. root 5738d 13h /xge_mac/trunk/rtl/auto_verilog.sh
2 Initial revision antanguay 6021d 01h /xge_mac/trunk/rtl/auto_verilog.sh

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