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[/] [xge_mac/] [trunk/] [rtl/] [auto_verilog.sh] - Rev 27

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24 Use FIFO's for statistics clock domain crossing antanguay 4385d 12h /xge_mac/trunk/rtl/auto_verilog.sh
23 Adding basic packet stats antanguay 4385d 18h /xge_mac/trunk/rtl/auto_verilog.sh
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4387d 15h /xge_mac/trunk/rtl/auto_verilog.sh
20 Updates for Xilinx synthesis antanguay 4677d 09h /xge_mac/trunk/rtl/auto_verilog.sh
7 New directory structure. root 5742d 02h /xge_mac/trunk/rtl/auto_verilog.sh
2 Initial revision antanguay 6024d 13h /xge_mac/trunk/rtl/auto_verilog.sh

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