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[/] [xge_mac/] [trunk/] [rtl/] [include/] [defines.v] - Rev 28

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Rev Log message Author Age Path
28 Adding parameter for max frame size antanguay 4330d 12h /xge_mac/trunk/rtl/include/defines.v
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4385d 13h /xge_mac/trunk/rtl/include/defines.v
24 Use FIFO's for statistics clock domain crossing antanguay 4385d 15h /xge_mac/trunk/rtl/include/defines.v
23 Adding basic packet stats antanguay 4385d 21h /xge_mac/trunk/rtl/include/defines.v
22 Added prototype system verilog testbench antanguay 4387d 17h /xge_mac/trunk/rtl/include/defines.v
12 Change interface to big endian, added serdes examples to testbench antanguay 5463d 20h /xge_mac/trunk/rtl/include/defines.v
7 New directory structure. root 5742d 05h /xge_mac/trunk/rtl/include/defines.v
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 6018d 13h /xge_mac/trunk/rtl/include/defines.v
2 Initial revision antanguay 6024d 16h /xge_mac/trunk/rtl/include/defines.v

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