URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_small.v] - Rev 27

Rev	Log message	Author	Age	Path
25	Timing improvements, reduced FIFO size from 1024 to 512	antanguay	4381d 17h	/xge_mac/trunk/rtl/verilog/generic_mem_small.v
22	Added prototype system verilog testbench	antanguay	4383d 21h	/xge_mac/trunk/rtl/verilog/generic_mem_small.v
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4383d 22h	/xge_mac/trunk/rtl/verilog/generic_mem_small.v
20	Updates for Xilinx synthesis	antanguay	4673d 16h	/xge_mac/trunk/rtl/verilog/generic_mem_small.v
7	New directory structure.	root	5738d 09h	/xge_mac/trunk/rtl/verilog/generic_mem_small.v
2	Initial revision	antanguay	6020d 20h	/xge_mac/trunk/rtl/verilog/generic_mem_small.v