URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [tx_dequeue.v] - Rev 27

Rev	Log message	Author	Age	Path
26	Fix packet count	antanguay	4381d 16h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
25	Timing improvements, reduced FIFO size from 1024 to 512	antanguay	4381d 17h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
24	Use FIFO's for statistics clock domain crossing	antanguay	4381d 19h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
23	Adding basic packet stats	antanguay	4382d 01h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4383d 22h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
20	Updates for Xilinx synthesis	antanguay	4673d 16h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
12	Change interface to big endian, added serdes examples to testbench	antanguay	5459d 23h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
10	Added details to spec	antanguay	5663d 16h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
7	New directory structure.	root	5738d 09h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	6014d 17h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
2	Initial revision	antanguay	6020d 20h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v