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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [tx_hold_fifo.v] - Rev 12

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Rev Log message Author Age Path
12 Change interface to big endian, added serdes examples to testbench antanguay 5459d 22h /xge_mac/trunk/rtl/verilog/tx_hold_fifo.v
7 New directory structure. root 5738d 07h /xge_mac/trunk/rtl/verilog/tx_hold_fifo.v
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 6014d 15h /xge_mac/trunk/rtl/verilog/tx_hold_fifo.v
2 Initial revision antanguay 6020d 19h /xge_mac/trunk/rtl/verilog/tx_hold_fifo.v

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