URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [tbench/] [verilog/] [tb_xge_mac.sv] - Rev 30

Rev	Log message	Author	Age	Path
30	Changes to testbench to support Icarus simulator	antanguay	4323d 18h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.sv
24	Use FIFO's for statistics clock domain crossing	antanguay	4385d 11h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.sv
23	Adding basic packet stats	antanguay	4385d 17h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.sv
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4387d 14h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.sv
17	Fixed deprecated SystemC warnings	antanguay	4855d 13h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.sv
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4855d 20h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.sv
14	Change interface to big endian, added serdes examples to testbench	antanguay	5463d 15h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.v
12	Change interface to big endian, added serdes examples to testbench	antanguay	5463d 15h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.v
7	New directory structure.	root	5742d 01h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.v
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	6018d 09h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.v
2	Initial revision	antanguay	6024d 12h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.v