URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [RAM.vhdl] - Rev 25

Rev	Log message	Author	Age	Path
25	Problem with memory: created conditional generate based upon data width instead of address width.	lcdsgmtr	3329d 06h	/xucpu/trunk/src/components/BRAM/RAM.vhdl
20	Update RAM package to allow for 15-bit address. Update test bench to use address width parameter.	lcdsgmtr	3329d 06h	/xucpu/trunk/src/components/BRAM/RAM.vhdl
17	Moving the generic block ram component piece by piece to a better implementation.	lcdsgmtr	3329d 06h	/xucpu/trunk/src/components/BRAM/RAM.vhdl
15	Unification of all RAM parts into one interface.	lcdsgmtr	3329d 06h	/xucpu/trunk/src/components/BRAM/RAM.vhdl
5	Re-organisation of repository.	lcdsgmtr	3463d 06h	/xucpu/trunk/src/components/BRAM/RAM.vhdl
2	First checkin to make sure that the project does not get stale.	lcdsgmtr	3585d 07h	/xucpu/trunk/VHDL/blockram/RAM.vhdl