URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [tb_generic_ram.vhdl] - Rev 24

Rev	Log message	Author	Age	Path
23	Currently moved test bench to 10 bit address. Created spreadsheet for filling memory with random data. When testing, memory is apparently not initialised.	lcdsgmtr	3204d 20h	/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl
20	Update RAM package to allow for 15-bit address. Update test bench to use address width parameter.	lcdsgmtr	3204d 20h	/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl
17	Moving the generic block ram component piece by piece to a better implementation.	lcdsgmtr	3204d 20h	/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl
5	Re-organisation of repository.	lcdsgmtr	3338d 20h	/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl
2	First checkin to make sure that the project does not get stale.	lcdsgmtr	3460d 21h	/xucpu/trunk/VHDL/blockram/tb_generic_ram.vhdl