| Rev |
Log message |
Author |
Age |
Path |
| 117 |
Updates, to include new README and bench/cpp/Makefile that doesnt depend upon
a static VERILATOR_ROOT location. |
dgisselq |
2963d 16h |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp |
| 115 |
Made the SDCard support dependent upon a XULA25 macro, which is defined at the
top of the file. Remove the XULA25 macro definition, and this will build
assuming a XULA9 configuration. |
dgisselq |
3056d 18h |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp |
| 113 |
Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache. |
dgisselq |
3056d 18h |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp |
| 112 |
Provides a simulated UART capability to the busmaster_tb simulation. |
dgisselq |
3058d 23h |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp |
| 106 |
Minor, inconsequential changes. |
dgisselq |
3065d 12h |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp |
| 96 |
Now accepts an SD-Card backing file, so that SD-Card reads *and* writes can be
tested. |
dgisselq |
3088d 16h |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp |
| 75 |
Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.) |
dgisselq |
3094d 13h |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp |
| 47 |
Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.) |
dgisselq |
3172d 17h |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
3180d 17h |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp |
| 31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3184d 16h |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp |
| 4 |
Here's an initial, albeit incomplete, build. |
dgisselq |
3255d 11h |
/xulalx25soc/trunk/bench/cpp/busmaster_tb.cpp |
