URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [bench/] [cpp/] [pipecmdr.h] - Rev 51

Rev	Log message	Author	Age	Path
47	Fixes the "NAN" clocks/second output, as well as making input timing come closer to a realistic timing. (I actually don't know what timing the JTAG port is providing, but ... the new timer is closer.)	dgisselq	3169d 01h	/xulalx25soc/trunk/bench/cpp/pipecmdr.h
37	These fixes were necessary to get the SDRAM into a working simulation capability. It is finally what it was supposed to be: cycle accurate. Sadly, to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having a problem with external input clocking in Verilator. This fixes it--but its a Verilator only change--to rtl/wbsdram.v that is.)	dgisselq	3177d 01h	/xulalx25soc/trunk/bench/cpp/pipecmdr.h
4	Here's an initial, albeit incomplete, build.	dgisselq	3251d 20h	/xulalx25soc/trunk/bench/cpp/pipecmdr.h