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[/] [xulalx25soc/] [trunk/] [rtl/] [busmaster.v] - Rev 113

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113 Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache.		 dgisselq 2878d 20h /xulalx25soc/trunk/rtl/busmaster.v
106 Minor, inconsequential changes. dgisselq 2887d 14h /xulalx25soc/trunk/rtl/busmaster.v
101 Fixed the `defines at the top so that this can be built without any CPU.
This was then used to measure the impact of the CPU on the entire build, as
you could now build with no CPU, and then with a CPU to compare.		 dgisselq 2887d 14h /xulalx25soc/trunk/rtl/busmaster.v
83 Fixes a bug in the LX9 build whereby the flash was never ever granted permission
to use the SPI port.		 dgisselq 2915d 19h /xulalx25soc/trunk/rtl/busmaster.v
74 Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged.		 dgisselq 2916d 15h /xulalx25soc/trunk/rtl/busmaster.v
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.		 dgisselq 2994d 19h /xulalx25soc/trunk/rtl/busmaster.v
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 3006d 17h /xulalx25soc/trunk/rtl/busmaster.v
18 Got the bitfile back up to speed at 80 MHz. dgisselq 3072d 18h /xulalx25soc/trunk/rtl/busmaster.v
9 Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz.		 dgisselq 3074d 16h /xulalx25soc/trunk/rtl/busmaster.v
6 Initial file load, likely to be buggy, but the initial load nonetheless. dgisselq 3077d 12h /xulalx25soc/trunk/rtl/busmaster.v
2 A very first, albeit incomplete, build. dgisselq 3077d 13h /xulalx25soc/trunk/rtl/busmaster.v

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