URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [busmaster.v] - Rev 32

Rev	Log message	Author	Age	Path
31	A bug fix, although one that rearranges the bus. The first four I/O locations have been adjusted. The new locations are reflected in wishbone.html. In addition, the PWM and UART devices no longer create bus errors when accessed. Finally, this version uses a `define XULA25 to determine whether or not to build for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define would be to place it into your Xilinx configuration, should you wish to build for the LX25.	dgisselq	3184d 20h	/xulalx25soc/trunk/rtl/busmaster.v
18	Got the bitfile back up to speed at 80 MHz.	dgisselq	3250d 21h	/xulalx25soc/trunk/rtl/busmaster.v
9	Bug fixes, optimizations, etc. as part of building for an actual hardware implementation. Most notably, the speed was lowered from 80MHz down to 76 MHz.	dgisselq	3252d 20h	/xulalx25soc/trunk/rtl/busmaster.v
6	Initial file load, likely to be buggy, but the initial load nonetheless.	dgisselq	3255d 16h	/xulalx25soc/trunk/rtl/busmaster.v
2	A very first, albeit incomplete, build.	dgisselq	3255d 16h	/xulalx25soc/trunk/rtl/busmaster.v