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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [cpudefs.v] - Rev 115

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113 Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache.		 dgisselq 3042d 07h /xulalx25soc/trunk/rtl/cpu/cpudefs.v
72 Sets XULA25 as the default. dgisselq 3080d 02h /xulalx25soc/trunk/rtl/cpu/cpudefs.v
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 3128d 03h /xulalx25soc/trunk/rtl/cpu/cpudefs.v
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.		 dgisselq 3158d 06h /xulalx25soc/trunk/rtl/cpu/cpudefs.v
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 3170d 04h /xulalx25soc/trunk/rtl/cpu/cpudefs.v
2 A very first, albeit incomplete, build. dgisselq 3241d 00h /xulalx25soc/trunk/rtl/cpu/cpudefs.v

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