URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [cpuops.v] - Rev 115

Rev	Log message	Author	Age	Path
113	Lots of updates, mostly focused on getting the XuLA board and CPU able to pass a comprehensive test suite. At this point, everything passes and logic usage is down even. Among the few changes includes the "break" bit in the uCC register, used to indicate a switch to supervisor mode occurred as a result of a user break, and the ability for the supervisor to clear the instruction cache.	dgisselq	3042d 05h	/xulalx25soc/trunk/rtl/cpu/cpuops.v
60	LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively.	dgisselq	3080d 01h	/xulalx25soc/trunk/rtl/cpu/cpuops.v
52	This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and prepares it for the 32x32 bit multiply instruction set change.	dgisselq	3128d 01h	/xulalx25soc/trunk/rtl/cpu/cpuops.v
46	This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v from working when long pipelined reads were interrupted by the necessity of a pair of refresh cycles.	dgisselq	3158d 04h	/xulalx25soc/trunk/rtl/cpu/cpuops.v
21	Files, not links, to replace what were once broken links in this project.	dgisselq	3232d 13h	/xulalx25soc/trunk/rtl/cpu/cpuops.v