URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [div.v] - Rev 115

Rev	Log message	Author	Age	Path
113	Lots of updates, mostly focused on getting the XuLA board and CPU able to pass a comprehensive test suite. At this point, everything passes and logic usage is down even. Among the few changes includes the "break" bit in the uCC register, used to indicate a switch to supervisor mode occurred as a result of a user break, and the ability for the supervisor to clear the instruction cache.	dgisselq	3042d 07h	/xulalx25soc/trunk/rtl/cpu/div.v
98	Updated copyright notices for the new year, to reflect that changes have been made in 2016.	dgisselq	3051d 02h	/xulalx25soc/trunk/rtl/cpu/div.v
61	Fixed the timing control wires: busy and valid will never both be true. Busy will be true (now) until valid is asserted, and busy will never not be asserted until valid is true.	dgisselq	3080d 03h	/xulalx25soc/trunk/rtl/cpu/div.v
21	Files, not links, to replace what were once broken links in this project.	dgisselq	3232d 14h	/xulalx25soc/trunk/rtl/cpu/div.v