URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [div.v] - Rev 67

Rev	Log message	Author	Age	Path
61	Fixed the timing control wires: busy and valid will never both be true. Busy will be true (now) until valid is asserted, and busy will never not be asserted until valid is true.	dgisselq	2919d 15h	/xulalx25soc/trunk/rtl/cpu/div.v
21	Files, not links, to replace what were once broken links in this project.	dgisselq	3072d 03h	/xulalx25soc/trunk/rtl/cpu/div.v