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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [div.v] - Rev 96

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61 Fixed the timing control wires: busy and valid will never both be true. Busy
will be true (now) until valid is asserted, and busy will never not be
asserted until valid is true.
dgisselq 3071d 00h /xulalx25soc/trunk/rtl/cpu/div.v
21 Files, not links, to replace what were once broken links in this project. dgisselq 3223d 12h /xulalx25soc/trunk/rtl/cpu/div.v

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