OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [idecode.v] - Rev 115

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
113 Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache.		 dgisselq 3042d 07h /xulalx25soc/trunk/rtl/cpu/idecode.v
98 Updated copyright notices for the new year, to reflect that changes have been
made in 2016.		 dgisselq 3051d 01h /xulalx25soc/trunk/rtl/cpu/idecode.v
86 Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth.		 dgisselq 3074d 05h /xulalx25soc/trunk/rtl/cpu/idecode.v
62 Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated.		 dgisselq 3080d 02h /xulalx25soc/trunk/rtl/cpu/idecode.v
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 3128d 03h /xulalx25soc/trunk/rtl/cpu/idecode.v
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.		 dgisselq 3138d 01h /xulalx25soc/trunk/rtl/cpu/idecode.v
50 Updates to fix some broken early branching code, both in idecode and pfcache. dgisselq 3147d 04h /xulalx25soc/trunk/rtl/cpu/idecode.v
26 Some bug fixes, and the long jump early branching integration. dgisselq 3171d 05h /xulalx25soc/trunk/rtl/cpu/idecode.v
23 This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update.		 dgisselq 3179d 15h /xulalx25soc/trunk/rtl/cpu/idecode.v
21 Files, not links, to replace what were once broken links in this project. dgisselq 3232d 14h /xulalx25soc/trunk/rtl/cpu/idecode.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.